Recently, LCD devices are being spotlighted as the next generation high-tech display devices due to their low consumption power, excellent portability, and high added value. The LCD device contains liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate. The LCD device uses a refraction difference due to anisotropy of the liquid crystal to display an image.
One LCD device currently in use is an active matrix liquid crystal display (AM-LCD) that contains TFTs and pixel electrodes arranged in a matrix. The AM-LCD has excellent resolution and displays moving images well. Hydrogenated amorphous silicon (a-Si:H) is mainly used in the TFT because it can be fabricated using a low temperature process and a cheap insulating substrate. However, hydrogenated amorphous silicon has an irregular atom arrangement, thus having weak Si—Si bonds and dangling bonds. Accordingly, the amorphous silicon is converted into a quasi-stable state when irradiated with light or a magnetic field is applied thereto. Therefore, when the amorphous silicon is utilized in a thin film transistor device, a problem regarding the stability is generated. Also, since the amorphous silicon has small field effect mobility (0.1-1.0 cm2/V*s), the amorphous silicon can not be used in a driving circuit.
Recently, an LCD device that uses a poly-silicon thin film transistor is being researched and developed. Since poly-silicon has a field effect mobility larger than that of amorphous silicon by 100 to 200 times, the response speed thereof is fast and the stability against temperature and light is excellent. Also, poly-silicon has an advantage in that a driving circuit can be formed on the same substrate.
The conventional method for fabricating a thin film transistor using poly-silicon for an LCD device will be explained in more detail with reference to the attached drawings as follows.
FIG. 1 is a schematic view showing an LCD device where a driving circuit portion is formed in accordance with the conventional art.
Referring to FIG. 1, a driving circuit portion 5 and a pixel portion 3 are formed on an insulating substrate 1. The pixel portion 3 is arranged at the center of the insulating substrate 1. Also, a gate driving circuit portion 5a and a data driving circuit portion 5b are respectively arranged at one side and another side of the pixel portion 3 perpendicular to each other. At the pixel portion 3, a plurality of gate lines 7 connected to the gate driving circuit portion 5a and a plurality of data lines 9 connected to the data driving circuit portion 5b crossed each other. A pixel electrode 10 is formed at a pixel region P defined by the area bounded by adjacent gate lines 7 and adjacent data lines 9. Also, a thin film transistor T connected to the pixel electrode 10 is formed at an intersection of each of the gate lines 7 and data lines 9.
The gate driving circuit portion 5a and the data driving circuit portion 5b are respectively connected to an external signal input terminal 12. The gate driving circuit portion 5a and the data driving circuit portion 5b control external signals inputted through the external signal input terminal 12 therein, and then supply display control signals and data signals to the pixel portion 3 through the gate lines 7 and the data lines 9.
A thin film transistor (not shown) having a complementary metal-oxide semiconductor (CMOS) structure as an inverter is formed in the driving circuit portion in order for the gate driving circuit portion 5a and the data driving circuit portion 5b to properly output inputted signals. The CMOS structure is used in a driving circuit portion thin film transistor requiring fast signal processing. The n and p type semiconductors in the CMOS structure are electrically controlled by a reciprocal complement method in order to control a current passing therethrough.
The n type TFT structure, the p type TFT structure of the driving circuit portion which are the CMOS structure, and a switching device of the pixel portion of the array substrate will be explained with reference to FIG. 2 as follows. FIG. 2 is a section view showing a switching device of a pixel portion and a thin film transistor having a CMOS structure of the driving circuit portion in accordance with the conventional art.
Referring to FIG. 2, in the conventional switching device I of the pixel portion, a buffer layer 25 formed of an inorganic insulating material such as SiO2 is formed on an entire surface of the substrate 20. A semiconductor layer 30 is formed on the buffer layer 25, and a gate insulating layer 45 is formed on an entire surface of the semiconductor layer 30.
A gate electrode 50 is formed on the gate insulating layer 45, and an inter-insulating layer is formed on the gate electrode 50. Semiconductor layer contact holes 73a and 73b for contacting the semiconductor layer 30 are formed at the gate insulating layer 45 and the inter-insulating layer 70. A source electrode 80a and a drain electrode 80b respectively connected to the semiconductor layer contact holes 73a and 73b and spaced from the gate electrode 50 with a certain interval are formed on the inter-insulating layer 70.
A passivation film 90 including a drain electrode contact hole 95 is formed on the drain electrode 80b, and a pixel electrode 97 connected to the drain electrode 80 through the drain electrode contact hole 95 is formed on the passivation film 90.
The semiconductor layer 30 positioned at a lower region of the gate insulating layer 45 corresponding to the gate electrode 50 forms an active layer 30a, and the semiconductor layer 30 positioned at lower regions of the gate insulating layer 45 contacting the source and drain electrodes 80a and 80b are n+ doped thereby to form an n-type ohmic contact layer 30c. An n− doped light doped drain (LDD) layer 30b is formed between the active layer 30a and the n-type ohmic contact layer 30c. The LDD layer 30b is doped with a low concentration to disperse hot carriers, thereby preventing current leakage and preventing the loss of turned-on current.
In more detail, a channel layer, an ohmic layer, an LDD layer, a gate, and source/drains of the thin film transistor having the CMOS structure of the driving circuit portion are formed by the same processes as those for forming a channel layer, an ohmic layer, an LDD layer, a gate, and source/drains of the switching device of the pixel portion. The thin film transistor having the CMOS structure of the driving circuit portion has a thin film transistor portion II including an n+ doped semiconductor layer 35, and a thin film transistor portion III including a p+ doped semiconductor layer 40. Reference numerals will be given to the same device in the order of II and III for the convenience.
The n-type semiconductor layer 35 and the p-type semiconductor layer 40 are formed on the transparent insulating substrate 20 on which the buffer layer 25 is formed with a predetermined gap, and the gate insulating layer 45 is formed on the entire surfaces of the n-type semiconductor layer 35 and the p-type semiconductor layer 40. Gate electrodes 55 and 60 are formed on the gate insulating layer 45.
The inter-insulating layer 70 including semiconductor layer contact holes 75a, 75b, 77a, and 77b is formed on the entire surface of the substrate on which the gate electrodes 55 and 60 are formed. Source electrodes 83a and 87a and drain electrodes 83b and 87b respectively contacting the n-type semiconductor layer 35 and the p-type semiconductor layer 40 through the semiconductor layer contact holes 75a, 75b, 77a, and 77b are formed on the inter-insulating layer 70. The passivation film 90 is formed on the entire surfaces of the source and drain electrodes 83a, 87a, 83b, and 87b. 
The n-type semiconductor layer 35 which is positioned at a lower region of the gate insulating layer 45 corresponding to the gate electrode 55 forms an active layer 30a, and the n-type semiconductor layer 35 positioned at lower regions of the gate insulating layer 45 contacting the source and drain electrodes 83a and 83b form an n+ doped n-type ohmic contact layer 35c. An n− doped light doped drain (LDD) layer 35b is formed between the active layer 35a and the n-type ohmic contact layer 35c 
In the p-type semiconductor layer 40, holes are the carriers. Thus, carrier degradation and current leakage are not large when compared with the n-type thin film transistor. Thus, formation of an LDD layer may be avoided. The semiconductor layer positioned at a lower region of the gate insulating layer 45 corresponding to the gate electrode 60 forms an active layer 40a, and peripheral regions of the active layer 40a form a p-type ohmic contact layer 40c. 
A method for fabricating the switching device of the pixel portion and the thin film transistor having a CMOS structure of the driving circuit portion in the conventional LCD device will be explained in more detail with reference to FIGS. 3, and 4A to 4H.
FIG. 3 is a flowchart showing a mask process applied to the method for fabricating the switching device of the pixel portion of a top gate structure and the thin film transistor having a CMOS structure of the driving circuit portion in the conventional LCD device. FIGS. 4A to 4H are sectional views respectively showing the fabrication process of the switching device of the pixel portion and the thin film transistor having a CMOS structure of the driving circuit portion in accordance with the conventional art.
Referring to FIG. 3, the conventional method for fabricating a thin film transistor for an LCD device is a first mask process for forming a semiconductor layer on a substrate (S10), a second mask process for forming gate electrodes of a pixel portion and a driving circuit portion on the semiconductor layer (S20), a third mask process for selectively doping n+ impurities at one side of the semiconductor layer of the pixel portion and the driving circuit portion (S30), a fourth mask process for selectively doping p+ impurities at another side of the semiconductor layer of the driving circuit portion (S40), a fifth mask process for forming source/drain contact holes for exposing the semiconductor layer on which the impurities are formed (S50), a sixth mask process for forming source/drain at the source/drain contact holes (S60), a seventh mask process for forming a contact hole on a passivation film formed on an entire surface of the substrate including the source/drain (S70), and an eighth mask process for forming a pixel electrode at the contact hole of the passivation film (S80).
The conventional method for fabricating a thin film transistor for an LCD device by the 8-mask process will be explained in more detail with reference to FIGS. 4A to 4H.
As shown in FIG. 4A, an inorganic insulating material such as SiO2 is deposited on an entire surface of a transparent insulating substrate 20, thereby forming a buffer layer 25. Then, amorphous silicon a-Si is deposited on the entire surface of the substrate 20 on which the buffer layer 25 is formed. The amorphous silicon a-Si is then dehydrogenated, and the dehydrogenated amorphous silicon a-Si is laser-crystallized, thereby crystallizing the amorphous silicon layer into a poly-silicon layer.
Then, the poly-silicon layer is patterned by the first mask process S10 thereby to form semiconductor layers 30, 35, and 40.
As shown in FIG. 4B, silicon oxide is deposited on the entire surface of the substrate 20 on which the semiconductor layers 30, 35, and 40 are formed thereby to form a gate insulating layer 45.
Then, a metal material such as Mo is deposited on the gate insulating layer 45 and gate electrodes 50, 55, and 60 are then formed thereon by the second mask process S20. An n− lightly doped drain (LDD) doping is performed on the entire surface of the substrate 20 by ion injection using the gate electrodes 50, 55, and 60 as masks. Semiconductor layers 30a, 35a, and 40a positioned below the gate electrodes 50, 55, and 60 of the pixel portion and the driving circuit portion are not doped, and semiconductor layers 30b, 35b, and 40b are n−-doped.
As shown in FIG. 4C, a photoresist PR is deposited on the entire surface of the n−-doped substrate 20, and a photoresist pattern 62 is formed by the third mask process S30. The PR pattern 62 is formed to shield not only the gate electrodes 50 and 55 of the I and II regions but also an upper portion of the gate insulating layer 45 extending from both sides of the gate electrodes 50 and 55 with a predetermined interval. Also, a PR pattern 63 is formed to completely shield not only the gate electrode 60 but also the gate insulating layer 45 corresponding to the semiconductor layer 40 in the p type thin film transistor portion III of the driving circuit portion.
Then, an n+ doping is performed on the entire surface of the substrate 20 on which the PR patterns 62 and 63 are formed by injecting a high concentration of ions. The semiconductor layer that is not shielded by the PR patterns 62 and 63 is n+ doped thereby to form n-type ohmic contact layers 30c and 35c. The semiconductor layers 30 and 35 of the I and II regions onto which an n− doping and an n+ doping have not been performed by the gate electrodes 50 and 55 form active layers 30a and 35a, and n− doped parts between the active layers 30a and 35a and the ohmic contact layers 30c and 35c form LDD layers 30b and 35b. 
As shown in FIG. 4D, a photoresist is deposited on the entire surface of the substrate 20 on which the n-type ohmic contact layers 30c and 35c are formed. Then, a PR pattern 65 for covering not only the gate electrodes 50 and 55 but also the gate insulating layer 45 corresponding to the semiconductor layers 30 and 35 is formed in the pixel portion I and a first device region II of the driving circuit portion by the fourth mask process. Also, the PR pattern is not formed on the gate insulating layer corresponding to the p-type semiconductor layer 40 of the second device region III of the driving circuit portion.
Then, a p+ doping is performed by injecting a high concentration of ions. In the III region, the semiconductor layer 40 onto which the ion-doping has not been performed by the gate electrode 60 forms an active layer 40a, and the p+ doped parts of the semiconductor layer 40 form p-type ohmic contact layers 40c. Then, the PR pattern 65 is removed.
As shown in FIG. 4E, an inorganic insulating material such as SiNx or SiO2 is deposited on the entire surface of the substrate 20 on which the p-type ohmic contact layers 40c are formed, thereby forming an inter-insulating layer 70. Then, the inter-insulating layer 70 and the gate insulating layer 45 are integrally etched by the fifth mask process, thereby forming semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, and 77b for partially exposing the ohmic contact layers 30c, 35c, and 40c to outside.
As shown in FIG. 4F, Mo and AlNd are sequentially deposited on the inter-insulating layer 70 on which the semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, and 77b are formed, and then are integrally etched by the sixth mask process, thereby forming source and drain electrodes 80a, 83a, 87a, 80b, 83b, and 87b connected to the ohmic contact layers 30c, 35c, and 40c through the semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, and 77b. 
As shown in FIG. 4G, a silicon nitride SiNx is deposited on the substrate 20 on which the source and drain electrodes 80a, 83a, 87a, 80b, 83b, and 87b are formed, and then is thermally-hydrogenated. Then, a passivation film 90 having a drain contact hole 95 is formed on the substrate 20 by the seventh mask process.
Even if the subsequent steps belong to the process for fabricating an array substrate, the steps will be briefly explained since the subsequent steps relate to the process for fabricating a thin film transistor.
As shown in FIG. 4H, an indium tin oxide (ITO) is deposited on the entire surface of the substrate on which the passivation film 90 is formed. Then, a pixel electrode 97 connected to a drain electrode 90b through the drain contact hole 95 is formed by the eight mask process.
As aforementioned, in the conventional switching device of the LCD device having an integral driving circuit therein and the fabrication method thereof, mask processes are performed 8 times. Since the mask process includes photo-resist coating, exposure, and development, the fabrication cost and the processing time are increased as the number of the mask processes is increased. As the result, the price competitiveness is degraded and the production yield is degraded. In addition, as the number of the mask processes is increased, the generation of defects in the thin film transistor is increased. Further, in fabricating the thin film transistor of a top-gate structure, an n+ doped ohmic contact layer may be lost by an over-etching when forming the semiconductor layer contact hole.